# Sangjae Park — Academic Homepage & Hardware Engineering Blog

> Ph.D. Student in Electrical and Computer Engineering at the University of Minnesota Twin Cities (advised by Prof. Zhenman Fang). Former SoC RTL Engineer at Anapass Inc. (5+ mass-production OLED TCON/TED ASIC tape-outs for Steam Deck and Samsung Galaxy-A series). M.S. & B.S. in ECE from Sungkyunkwan University (SKKU).

- Homepage: https://sangjae4309.github.io/
- Email: park3376@umn.edu
- CV (PDF): https://sangjae4309.github.io/files/sangjae_park_cv.pdf
- Google Scholar: https://scholar.google.com/citations?user=6GTDVXwAAAAJ&hl=en
- GitHub: https://github.com/sangjae4309
- LinkedIn: https://www.linkedin.com/in/sangjae4309/

## Research & Technical Expertise

- **FPGA & High-Level Synthesis (HLS):** FPGA-based AI accelerators, HLS physical co-optimization, design space exploration (DSE), multi-die SLR timing closure.
- **SoC RTL & ASIC Design:** SystemVerilog microarchitecture, ready/valid skid buffers, Clock-Domain Crossing (CDC), VESA Display Stream Compression (DSC) codec, eDP/MIPI high-speed interfaces, Design-for-Test (DFT), and post-silicon yield debugging.
- **Memory Systems & Reliability:** On-die ECC, DRAM fault tolerance, dynamic remapping caches.

## Peer-Reviewed Publications

- **SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection**
  - Authors: Yuseok Song, Sangjae Park, Michael B. Sullivan, Jungrae Kim
  - Venue: IEEE Access, Vol. 10, 2022
  - DOI: https://doi.org/10.1109/ACCESS.2022.3201525
  - PDF: https://sangjae4309.github.io/pubs/SEC-BADAEC_An_Efficient_ECC_With_No_Vacancy_for_Strong_Memory_Protection.pdf
  - Summary: Proposes SEC-BADAEC, a zero-vacancy on-die Error Correction Code (ECC) that corrects both single-bit errors and byte-aligned double-adjacent errors (BADAEs) without additional redundancy.

- **On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults**
  - Authors: Sangjae Park, Jungrae Kim
  - Venue: IEEE Access, Vol. 10, 2022
  - DOI: https://doi.org/10.1109/ACCESS.2022.3192879
  - PDF: https://sangjae4309.github.io/pubs/On-Die_Dynamic_Remapping_Cache_Strong_and_Independent_Protection_Against_Intermittent_Faults.pdf
  - Summary: Proposes On-Die Dynamic Remapping Cache (OD-DRC), an autonomous in-DRAM remapping cache architecture that tracks and repairs intermittent and multi-bit faults to improve device-level reliability.

## Technical Blog Posts & Engineering Notes

- [Practical RTL & FPGA Design Principles: Skid Buffers, CDC, Datapath Pipelining & HLS](https://sangjae4309.github.io/blog/rtl-fpga-design-principles/) (2026-10-25)
  - Tags: RTL Design, FPGA & HLS, SoC Architecture, Timing Closure
  - Summary: Actionable hardware design principles covering zero-bubble ready/valid skid buffers, multi-bit CDC synchronization across eDP/MIPI video domains, VESA DSC datapath pipelining, physical-aware FPGA HLS pragma design, and post-silicon DFT observability.
  - Key Takeaways:
    * Break combinational ready-backpressure paths across SoC module boundaries using 2-entry registered skid buffers to preserve II=1 throughput while isolating timing paths.
    * Never double-flop multi-bit control buses across asynchronous pixel/system clock domains (eDP/MIPI to core clock); use Gray-coded asynchronous FIFOs or closed-loop req/ack handshakes.
    * In high-throughput codecs like VESA DSC, balance combinational logic depth explicitly in RTL rather than relying solely on synthesis retiming across clock-gated boundaries.
    * When writing FPGA High-Level Synthesis (HLS) kernels, treat C++ loops and hls::stream channels as physical hardware: co-optimize array partitioning and Super Logic Region (SLR) crossing registers early.
    * Build lightweight post-silicon observability (sticky protocol-violation flags, FIFO high-watermark registers, and muxed debug buses) into every IP block before tape-out.

- [CS231n Solution for Spring 2025: Vectorized Backprop, im2col CNNs, Multi-Head Attention & DDPM](https://sangjae4309.github.io/blog/cs231n-spring-2025-solution/) (2026-03-15)
  - Tags: Deep Learning, CS231n, Vectorization, PyTorch
  - Summary: Detailed walkthrough of Stanford CS231n (Spring 2025): no-loop KNN & Softmax gradients, Batch Normalization computation graphs, im2col convolutional forward/backward passes, Multi-Head Self-Attention, SimCLR InfoNCE loss, and DDPM.
  - Key Takeaways:
    * Replace explicit Python loops in KNN and Softmax classifiers with matrix expansion and in-place probability matrix adjustments for orders-of-magnitude faster execution.
    * Derive Batch Normalization and Spatial Batch/Group Normalization backward gradients systematically by decomposing the computational graph into intermediate partial derivatives.
    * Accelerate 2D convolutions and their backward passes (dW, dX) via im2col receptive-field matrix unrolling and dilated upstream gradients for strided convolutions.
    * Implement batched Multi-Head Self-Attention, vectorized SimCLR InfoNCE contrastive loss, and closed-form DDPM forward/reverse sampling steps.