Sangjae Park

Sangjae Park

Hello!

👋 I am a Ph.D. student in Electrical and Computer Engineering at the University of Minnesota Twin Cities, advised by Professor Zhenman Fang. My research lies in FPGA-based AI accelerators, High-Level Synthesis (HLS) physical co-optimization, and design space exploration.

Prior to starting my Ph.D. at UMN, I built a strong professional background in ASIC design, working as an SoC RTL Engineer at Anapass Inc. where I contributed to over 5 mass-production tape-out projects. This role also served as my alternative mandatory military service required of all Korean men. I received both my B.S. and M.S. degrees from Sungkyunkwan University (SKKU), where I conducted research on DRAM reliability under Professor Jungrae Kim.

In my free time, I love playing sports, particularly running, baseball, and soccer.

Education

University of Minnesota

Ph.D. Student in Electrical and Computer Engineering, University of Minnesota Twin Cities

Aug 2026 – Present, Minneapolis, MN

Advisor: Prof. Zhenman Fang

Sungkyunkwan University

M.S. in Electrical and Computer Engineering, Sungkyunkwan University (SKKU)

Jan 2021 – Jan 2023, Suwon, Korea

Thesis: On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults (Advisor: Prof. Jungrae Kim)
GPA: 4.44 / 4.5 (= 4.0 / 4.0)

Sungkyunkwan University

B.S. in Electrical and Electronic Engineering, Sungkyunkwan University (SKKU)

Mar 2017 – Jan 2021, Suwon, Korea

GPA: 3.75 / 4.5 (= 3.53 / 4.0), Major GPA: 4.03 / 4.5 (= 3.73 / 4.0)

Work Experience

Anapass Inc.

SoC RTL Engineer @ R&D Center, Anapass Inc.

Jan 2023 – Jun 2026, Seoul, Korea

  • Served in this position as an alternative to the mandatory military duty required of all Korean males.
  • Products: OLED TCON/TED ASICs developed in collaboration with Samsung Display and adopted in major consumer devices such as Steam Deck and Samsung Galaxy-A series (5+ mass-production tape-outs).
  • Primary responsibilities centered on DFT, DSC codec, and Gate Pulse I/O, with a working understanding of both eDP and MIPI interfaces.
  • Played a key role in resolving yield-loss issues via post-silicon debugging, working closely with manufacturing teams.

Publications

SEC-BADAEC architecture SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection
Yuseok Song, Sangjae Park, Michael B. Sullivan, Jungrae Kim
IEEE Access, Vol. 10, 2022

We propose SEC-BADAEC, a zero-vacancy on-die Error Correction Code (ECC) that corrects both single-bit errors and byte-aligned double-adjacent errors (BADAEs) without additional redundancy. [paper] [pdf]

On-Die Dynamic Remapping Cache overview On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults
Sangjae Park, Jungrae Kim
IEEE Access, Vol. 10, 2022

We propose On-Die Dynamic Remapping Cache (OD-DRC), an autonomous in-DRAM remapping cache architecture that tracks and repairs intermittent and multi-bit faults to improve device-level reliability. [paper] [pdf]