Notes & Articles

Notes on RTL/SoC microarchitecture, FPGA & High-Level Synthesis (HLS), and deep learning systems.

Oct 25, 2026 · 7 min read · RTL Design / FPGA & HLS / SoC Architecture / Timing Closure

Practical RTL & FPGA Design Principles: Skid Buffers, CDC, Datapath Pipelining & HLS

Actionable hardware design principles covering zero-bubble ready/valid skid buffers, multi-bit CDC synchronization across eDP/MIPI video domains, VESA DSC datapath pipelining, physical-aware FPGA HLS pragma design, and post-silicon DFT observability.

Mar 15, 2026 · 14 min read · Deep Learning / CS231n / Vectorization / PyTorch

CS231n Solution for Spring 2025: Vectorized Backprop, im2col CNNs, Multi-Head Attention & DDPM

Detailed walkthrough of Stanford CS231n (Spring 2025): no-loop KNN & Softmax gradients, Batch Normalization computation graphs, im2col convolutional forward/backward passes, Multi-Head Self-Attention, SimCLR InfoNCE loss, and DDPM.